The present invention relates to a multi-place ripple-carry adder and more particularly to such an adder which can be embodied in an integrated circuit, using CMOS technology and which is adapted to receive an input carry signal in one polarity and produce an output carry signal which is in the inverted polarity.
Adders are required in a large number of digital logic circuits, for example digital filters, signal processors, and microprocessors. The simplest form for such an adder employs the ripple-carry method, in which a carry signal is serially transmitted from an adder cell for a lower order bit to the adder cell for the next higher order bit. The propagation time for the carry signal essentially defines the addition time. More involved adder constructions such as, for example, the known look-ahead method, are based on elements of the ripple-carry method.
Ripple-carry cells are known, for example from H. W. Weiss, K. Horninger, "Integrierte MOS-Schaltungen", Springer-Verlag, Berlin-Heidelberg, New York (1982), pp. 188-194. In existing adder cell designs, the propagation time required for the carry is a critical factor in the calculating time of an arithmetic unit constructed with such adder cells, and a relatively large number of gates are inserted into the carry propagation path, or the gates in the carry paths are components parts of combination gates. In the former case, the number of gates connected in series has an unfavorable effect on the propagation time of carry signals. In the second case, there is also the unfavorable effect that charging the capacitance of the carry output does not take place with the required edge steepness, due to the relatively high impedance of the gates which are formed as component parts of combination gates.